نوع مقاله : مقاله پژوهشی
عنوان مقاله English
نویسنده English
In this paper, a fractional-N PLL synthesizer with a closed-loop bandwidth of 200 Khz has been designed and simulated. This synthesizer is very useful for simulating the phase-locked loop system in the application of radar and satellite technology. The numerical values of the ring filter block, which is essential for locking the entire set, have been calculated using MATLAB software. Also, according to the working frequency, the number and distance of the channels, a high-speed frequency divider circuit has been designed. To generate fractional division values, sigma-delta modulator with MASH 1-1-1 arrangement is used. The operation speed of the loop is also considered a suitable parameter for satellite application. Also, sub-blocks have been used to reduce the delay and power consumption, which are the main goals of this article. From the results of the circuit implementation, we can mention the locking time of the entire PLL loop in 3 usec, as well as the open loop phase noise of 45 degrees
کلیدواژهها English
